Image sensor with pixels having multiple capacitive storage elements

ABSTRACT

An apparatus has a pixel that includes (i) a buffer transistor having an input, (ii) first and second capacitive storage elements each of which selectively can be coupled to the input of the buffer transistor, and (iii) a photosensitive element having an output which selectively can be coupled to the input of the buffer transistor. A readout circuit selectively can be coupled to an output of the buffer transistor. A first signal level, sensed by the photosensitive element, can be stored by the first capacitive storage element, and a second signal level, sensed by the photosensitive element, can be stored by the second capacitive storage element. The first and second signal levels can be read out from the pixel.

BACKGROUND

The present invention relates to image sensors with pixels havingmultiple capacitive storage elements.

Image sensors can be used in a wide variety of fields, including machinevision, robotics, guidance and navigation, automotive applications, andconsumer products. They can include on-chip circuitry that controlsimage sensor operation, signal read-out and image processing functions.Image sensors can utilize, for example, active pixel sensor (APS)technology with each active pixel sensor including one or more activetransistors. Each pixel sensor element can provide an output value thatrepresents a particular portion of an image.

SUMMARY

An apparatus, such as an imager, includes a pixel that has (i) a buffertransistor having an input, (ii) first and second capacitive storageelements each of which selectively can be coupled to the input of thebuffer transistor, and (iii) a photosensitive element having an outputwhich selectively can be coupled to the input of the buffer transistor.The apparatus also includes a readout circuit that selectively can becoupled to an output of the buffer transistor.

A first signal level, sensed by the photosensitive element, can bestored by the first capacitive storage element, and a second signallevel, sensed by the photosensitive element, can be stored by the secondcapacitive storage element. The first and second signal levels can beread out from the pixel.

In various implementations, the apparatus may include one or more of thefollowing features. A first switch can be coupled between the output ofthe photosensitive element and the input of the buffer transistor. Asecond switch can be coupled between the first capacitive storageelement and the input of the buffer transistor, and a third switch canbe coupled between the second capacitive storage element and the inputof the buffer transistor. A fourth switch can be coupled between a powersupply node and the input of the buffer transistor. Each of the switchescan be selectively operable in an open or closed state.

A controller can provide signals to control the respective states of thefirst, second, third and fourth switches. The controller can beconfigured to provide signals to cause the first capacitive storageelement to store a first signal level sensed by the photosensitiveelement during a first integration time and to cause the secondcapacitive element to store a second signal level sensed by thephotosensitive element during a second integration time. For example,the controller can be configured to provide signals to cause (i) thefirst and second switches to be closed during the first integrationtime, (ii) the third and fourth switches to be open during the firstintegration time, (iii) the first and third switches to be closed duringthe second integration time, and (iv) the second and fourth switches tobe open during the second integration time.

The controller also can be configured to provide signals to reset thephotosensitive element and the first capacitive storage element prior tothe first integration period and to reset the photosensitive element andthe second capacitive storage element prior to the second integrationperiod. For example, the controller can be configured to provide signalsto cause (i) the first, second and fourth switches to be closed justprior to the first integration period, and (ii) the first, third andfourth switches to be closed just prior to the second integrationperiod.

The controller can be configured for providing signals to selectivelytransfer the first signal level from the first capacitive storageelement to the readout circuit and to transfer the second signal levelfrom the second capacitive element to the readout circuit. Furthermore,the controller can be configured to provide signals to reset the inputof the buffer transistor prior to transferring the first signal levelfrom the first capacitive storage element to the readout circuit and toreset the input of the buffer transistor prior to transferring thesecond signal level from the second capacitive storage element to thereadout circuit. Thus, the controller can be configured to providesignals to cause the fourth switch to be closed prior to transferringthe first signal level from the first capacitive storage element to thereadout circuit and to cause the fourth switch to be closed just priorto transferring the second signal level from the second capacitivestorage element to the readout circuit.

In some implementations, the reset switch is configured for operation ina sub-threshold reset mode.

An integrated circuit can include an array of pixels each of whichincludes multiple capacitive storage elements. Readout circuitryselectively can be coupled to outputs of buffer transistors of selectedpixels in the array. The pixels, as well as the controller and thereadout circuitry, can be formed as part of a monolithic integratedcircuit.

One or more of the following advantages may be present in someimplementations. Signals representing the difference between twoexposures can be obtained without measuring pixel reset values.Eliminating measurement of pixel reset levels can help reduce the noisethat is inherent in such measurements. Additional reductions in thermalor “kTC” noise can be achieved by operating the reset switch insub-threshold mode.

Other features and advantages will be readily apparent from thefollowing detailed description, the accompanying drawings and theclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a system block diagram of an integrated circuit chip.

FIG. 2 illustrates further details of the integrated circuit chip.

FIG. 3 is a schematic diagram of a pixel and an associated columnreadout circuit.

FIG. 4 is a timing diagram of signals associated with FIG. 3.

FIG. 5 is a schematic diagram of a pixel.

DETAILED DESCRIPTION

As shown in FIG. 1, a monolithic integrated imaging circuit chip 10includes an array of active pixel sensors 30 and a controller 32 thatprovides timing and control signals to control operation of the pixelsand enable reading out of signals stored in the pixels. The array 30 mayhave dimensions of 128 by 128 pixels or 256 by 256 pixels, although, ingeneral, the size of the array will depend on the particularimplementation. The imager can be read out a row at a time using aparallel column readout architecture. The controller 32 selects aparticular row of pixels in the array 30 by controlling the operation ofa vertical addressing circuit 34 and row drivers 40. Charge signalsstored in the selected row of pixels are transferred to a readoutcircuit 42. The pixels read from each of the columns then can be readout sequentially using a horizontal addressing circuit 44. Adifferential signal for each pixel can be provided at an output of thereadout circuit 42.

As shown in FIG. 2, the array 30 includes multiple columns 49 of activepixel sensors 50. Each column includes multiple rows of sensors 50.Signals from the active pixel sensors 50 in a particular column can beread out to a readout circuit 52 associated with that column. Forexample, pixel signal levels corresponding to different exposure timesmay be stored by the readout circuit 52 and then transferred to a commonoutput stage 54 over lines 70, 72. The output stage 54 can provide adifferential signal corresponding to the difference between the pixelsignals obtained during the different exposure times.

As shown in FIG. 3, a single CMOS active pixel sensor 50 includes aphoto-sensitive element 60 buffered by a source-follower transistor M1.The source-follower transistor M1 is coupled to a power supply voltage(vdd) and to a row selection switch which can be implemented by atransistor M2. A signal (ROW) is applied to the gate of the rowselection transistor M2 to enable reading out of signals from a pixel inthe selected row. The row selection signal (ROW) is common to an entirerow of pixels. In one implementation, the photosensitive element 60includes a photogate. A floating diffusion node 62 that serves as asense node is coupled to the gate of the source-follower M1 and isseparated from the photosensitive element 60 by a transfer gate S1. Thepixel 50 includes a reset switch S4 that can be implemented as atransistor. When the reset switch S4 is closed, it is coupled to a powersupply voltage (Vrst).

The pixel includes storage capacitors C1, C2 for storing charge orvoltage signals corresponding to optical signals sensed by thephotosensitive element 60. Respective switches S2, S3, which can beimplemented as transistors, are coupled between the floating diffusionnode 62 and the capacitors C1, C2. The values of the capacitors C1, C2should be substantially the same.

As illustrated by FIG. 3, output signals from a pixel 50 can be providedto the readout circuit 52 through a bus 64 that is common to an entirecolumn 49 of pixels. The readout includes a load transistor M5 and twosample and hold switches M3, M4, which can be implemented astransistors. The switch M3 is controlled by a signal (SHS) applied toits gate, whereas the switch M4 is controlled by a signal (SHR). When asample and hold switch is closed, a voltage signal that is present onthe common pixel output bus 64 is stored by the corresponding capacitor.For example, when the switch M3 is closed, a voltage signal that ispresent on the bus 64 is stored by the capacitor C3. Similarly, when theswitch M4 is closed, a voltage signal that is present on the bus 64 isstored by the capacitor C4.

Signals for controlling the state of the various switches are providedby the controller 32. For purposes of the following discussion, it isassumed that each switch is implemented as an n-type metal oxidesemiconductor (NMOS) transistor switch such that the switch is open whenits control signal is high and is closed when its control signal is low.The reverse is applicable to p-type MOS (PMOS) switches.

In operation, the photosensitive element 60 and the first storagecapacitor C1 are reset by closing and subsequently opening the resetswitch S4 while the switches S1 and S2 are closed. As shown, forexample, in FIG. 4, the reset switch S4 is closed at time t₁ andsubsequently opened at time t₂. Switches S1 and S2 remain closed tointegrate photocharge on the first capacitor C1 during a firstintegration period. The first integration period ends at time t₃ whenthe switches S1 and S2 are closed. Next, the photosensitive element 60and the second storage capacitor C2 are reset by closing andsubsequently opening the reset switch S4 while the switches S1 and S3are opened. As shown in FIG. 4, the reset switch S4 is closed at time t₄and subsequently opened at time t₅. Switches S1 and S3 remain closed tointegrate photocharge on the first capacitor C2 during a secondintegration period. The second integration period ends at time t₆ whenthe switches S1 and S3 are opened. The first and second integrationperiods correspond to first and second exposure periods, respectively.The imager can be operated in shutter mode with common integrationperiods for the entire array of pixels.

After completion of the two exposure periods, the row selection signal(ROW) enables (at time t₇) a pixel in the selected row to be coupledelectrically to the column bus 64. The pixel's floating node 62 is resetby closing reset switch S4 at time t₈. After re-opening switch S4 (attime t₉), the signal stored by the first capacitor C1 is transferred tothe source follower M1 by closing the switch S2 (at time t₁₀). The pixelsignal corresponding to the first exposure time passes through the rowselection switch M2 to the bus 64. The sample and hold switch M3 also isenabled at time t₁₀, thereby allowing the pixel signal for the firstexposure time to be sampled and stored by the capacitor C3. At time t₁₁,the switch S2 and the switch M3 are opened.

The pixel's floating node 62 again is rest by closing reset switch S4 attime t₁₂. After re-opening switch S4 (at time t₁₃), the signal stored bythe first capacitor C2 is transferred to the source follower M1 byclosing the switch S3 (at time t₁₄). The pixel signal corresponding tothe second exposure time passes through the row selection switch M2 tothe bus 64. The sample and hold switch M4 also is enabled at time t₁₄,thereby allowing the pixel signal for the second exposure time to besampled and stored by the capacitor C4. At time t₁₅, the switch S3 andthe switch M4 are opened.

The signals stored by the capacitors C3 and C4 can be read out,respectively, through lines 70, 72 to the output stage 54 which includescircuitry for determining the difference between the input signals.Thus, the output signals from stage 54 represent the difference betweenthe images sensed and stored by the pixel during the two exposure times.The output signals can be converted to corresponding digital signalsusing an analog-to-digital converter (ADC). The signals from the otherpixels in the selected row can be read out sequentially. Alternatively,a separate output stage 54 and ADC can be provided for each column orblock of columns to provide parallel readout.

After processing the signals from the pixels in the selected row,another row of pixels can be selected to allow the stored signal levelsto be read out and processed.

One advantage that may be achieved through the foregoing technique isthe ability to obtain differential values representing the differencebetween two exposures without measuring pixel reset values. Eliminatingmeasurement of pixel reset levels can help reduce the noise that isinherent in such measurements. Nevertheless, the pixel design describedabove also can be used to obtain differential values representing thedifference between the pixel signal level and pixel reset level.

Additional reductions in thermal or “kTC” noise can be achieved byoperating the reset switch S4 in soft, or sub-threshold, reset mode. Inthat case, as illustrated in FIG. 5, the switch S4 should be implementedas an NMOS transistor, whereas the switches S1, S2 and S3 should beimplemented as PMOS transistors operating in linear triode mode toensure complete transfer of signals between the photosensitive element60, the capacitive storage memories C1 and C2, and the source followerM1.

Other implementations are within the scope of the claims.

1-30. (canceled)
 31. An imager, comprising: a pixel, comprising: afloating diffusion region, a source follower transistor having a gateconnected to said floating diffusion region, a first capacitive storageelement that can be selectively coupled to the floating diffusion regionthrough a first switchable element, a second capacitive storage elementthat can be selectively coupled to the floating diffusion region througha second switchable element, and a photosensitive element which can becoupled to said floating diffusion region; and a signal generator forproviding timing signals to control said switchable elements such thatsaid first switchable element is on and said second switchable elementis off to cause photo generated charges provided by the photosensitiveelement to accumulate at said floating diffusion region having saidfirst capacitive storage element coupled thereto during a firstintegration period, and following said first integration period, saidfirst switchable element is off and second switchable element is on tocause photo generated charges provided by the photosensitive element toaccumulate at said floating diffusion region having said secondcapacitive storage element coupled thereto during a second integrationperiod.
 32. The imager of claim 31, wherein the pixel further comprises:a third switchable element for selectively coupling the photosensitiveelement to said floating diffusion region.
 33. The imager of claim 32,wherein the pixel further comprises: a fourth switchable element forselectively resetting said floating diffusion region.
 34. The imager ofclaim 33, wherein said signal generator is operable to cause the firstand third switchable elements to be on to cause photo generated chargesprovided by the photosensitive element to accumulate at said floatingdiffusion region having said first capacitive storage element coupledthereto during said first integration period.
 35. The imager of claim33, wherein said signal generator is operable to cause the second andthird switchable elements to be on to cause photo generated chargesprovided by the photosensitive element to accumulate at said floatingdiffusion region having said second capacitive storage element coupledthereto during said second integration period.
 36. The imager of claim33, wherein said signal generator is operable to cause said floatingdiffusion region to be reset a first time with said fourth switchableelement before the first integration period.
 37. The imager of claim 36,wherein said signal generator is operable to cause said floatingdiffusion region to be reset a second time with said fourth switchableelement after the first integration period and before the secondintegration period.
 38. The imager of claim 31, further comprising: areadout line selectively coupled to an output of said source followertransistor for receiving pixel output signals, which include a firstoutput signal based on photo generated charges accumulated during saidfirst integration period and a second output signal based on photogenerated charges accumulated during said second integration period. 39.The imager of claim 33, wherein the fourth switchable element isconfigured for operation in a sub-threshold reset mode.
 40. Anintegrated circuit comprising: an array of pixels, each of which isassociated with a respective row and column in the array, the pixelscomprising: a floating diffusion region, a source follower transistorhaving a gate connected to said floating diffusion region, a firstcapacitive storage element that can be selectively coupled to thefloating diffusion region through a first switchable element, a secondcapacitive storage element that can be selectively coupled to thefloating diffusion region through a second switchable element, aphotosensitive element that can be selectively coupled to said floatingdiffusion region through a third switchable element, and a fourthswitchable element for selectively resetting said floating diffusionregion; a signal generator for providing timing signals to control saidswitchable elements such that said first and third switchable elementsare on while said second switchable element is off to cause photogenerated charges provided by the photosensitive element to accumulateat said floating diffusion region having said first capacitive storageelement coupled thereto during a first integration period, and followingsaid first integration period, said second and third switchable elementsare on while said first switchable element is off to cause photogenerated charges provided by the photosensitive element to accumulateat said floating diffusion region having said second capacitive storageelement coupled thereto during a second integration period; and areadout line selectively coupled to an output of said source followertransistor for receiving pixel output signals, which include a firstoutput signal based on the photo generated charges accumulated duringthe first integration period and a second output signal based on photogenerated charges accumulated during the second integration period. 41.The integrated circuit of claim 40, wherein said signal generator isoperable to cause said floating diffusion region is reset a first timewith said fourth switchable element before the first integration periodand said floating diffusion region is reset a second time with saidfourth switchable element after the first integration period and beforethe second integration period.
 42. The integrated circuit of claim 40,wherein the fourth switchable element is configured for operation in asub-threshold reset mode.
 43. A method comprising: continuouslytransferring charge collected by a photosensitive element during a firstintegration period to a first capacitive storage element; continuouslytransferring charge collected by the photosensitive element during asecond integration period to a second capacitive storage element;converting the charge stored on the first capacitive storage element toa first signal and reading out the first signal; and converting thecharge stored on the second capacitive storage element to a secondsignal and reading out the second signal.
 44. The method of claim 43,further comprising resetting the photosensitive element and the firstcapacitive storage element prior to the first integration period. 45.The method of claim 44, further comprising resetting the photosensitiveelement and the second capacitive storage element prior to the secondintegration period.
 46. The method of claim 43, further comprisingobtaining a signal representing the difference between the first andsecond signals read from the pixel.
 47. The method of claim 43, furthercomprising reading out the first and second signals from the pixelthrough a source follower transistor by resetting floating diffusionregion coupled to a gate of the source follower transistor prior toreading out the first signal from the first capacitive storage element;and resetting the gate of the source follower transistor prior toreading out the second signal from the second capacitive storageelement.
 48. The method of claim 43 including operating a pixel resetswitch in a sub-threshold reset mode.